| Intel Nehalem technology officer tell you what | | | | comparable FSB . QPI is the first to give them a |
| If we pay attention to the words, Nehalem word | | | | splendor to support multiple processor server |
| appears in the frequency of IT related media more | | | | platforms, QPI can be used for the interconnection |
| and more, Nehalem What stuff? Nehalem is Intel's next | | | | between multiple processors. |
| generation CPU micro-architecture of the code, the | | | | Currently, the Bloomfield-based Nehalem |
| code itself is of little practical significance. The correct | | | | micro-architecture processor (Bloomfield is also the |
| expression on the Nehalem should be: the new Core | | | | product code) has been officially named "Core i7". |
| microarchitecture. | | | | Core is the brand, "i7" is the series number. Core to this |
| As "Tick-Tock" strategy of product and technology | | | | name now and in the future will be Intel's flagship PC |
| development in even years HP pavilion ze4400 | | | | processor brand. |
| battery, Intel this year released a major technological | | | | The first processor based on Nehalem |
| advances is a new generation CPU microarchitecture | | | | micro-architecture will be used for desktop processors |
| ---- Nehalem, the next-generation micro-architecture | | | | Core i7, supported chipset is x58. This processor has |
| microprocessors joined more to improve performance, | | | | four cores, programs listed in the fourth quarter of this |
| energy-saving control, multi-processor expansion | | | | year. For servers and laptops Nehalem |
| capability and efficiency balanced design. | | | | microarchitecture will be listed in the future. |
| Nehalem micro-architecture is divided into two main | | | | Intel product code or item code for the origin of |
| parts: the calculation of core and non-computing kernel | | | | Familiar with Intel's probably all know each |
| 1. Calculated from the previous core micro-architecture | | | | representative of Intel products, or when the |
| design and optimization was carried out and | | | | technology has in the development of a product code |
| strengthened, mainly the following aspects: | | | | or item code. These codes will not be used for official |
| (1) Support Hyper-Threading Technology | | | | product launch will be used for the development phase |
| Hyper-Threading ---- third-generation, quad-core thread | | | | of the communication. |
| when as many as eight. | | | | Intel products to market using the official brand and |
| (2) supporting virtual device I / O (VT-d )---- before the | | | | product names identified much later than the product |
| virtualization in the CPU-based devices based on the | | | | of the project and development phase, the product |
| increase in input / output virtualization, virtual machine | | | | brand and product names are too many aspects |
| can improve performance and efficiency. | | | | involved, such as legal aspects: trade mark registration, |
| (3) core speed mode (Turbo Mode )---- kernel running | | | | scope of use; the humanities : the user acceptance |
| dynamic acceleration. As needed to open, close, and | | | | and so on. |
| speed up the operation of a single kernel. For example, | | | | Therefore, for communication, then they use the code |
| in a quad-core Nehalem micro-architecture processor, | | | | to communicate, Intel's right to choose the code to the |
| if a task requires only two cores, can close the other | | | | project group or project's responsible person, Ta Men |
| two cores running at the same time work to run two | | | | can Genju You like to Ji new products and new |
| core clock speed increase. If the task requires only a | | | | technologies take a code. However, the naming is not |
| kernel, you can turn off the other three cores, while the | | | | an exercise in imagination, has a premise, in order to |
| work of a core to a higher frequency operation. This | | | | avoid potential legal risks, the choice should be the |
| dynamic adjustment can improve the system and the | | | | code name can be found on the map. |
| CPU rate of the overall energy efficiency. | | | | Intel a lot of product development departments are |
| (4) the new SSE 4.2 instruction set and so on. | | | | concentrated in California (California) Silicon Valley near |
| 2. Non-core design changes calculated impressive, and | | | | San Francisco and Oregon (Oregon) Portland around, |
| they are: | | | | so the two parts of the project team will work with |
| (1) Cache Design ---- with all three Cache design | | | | Intel to work around the place names, street name, |
| includes style, L1 Core micro-architecture design and | | | | river name, of mountains, etc. as a product or project |
| the same; L2 ultra-low latency design, each core | | | | code, which can be found on the map. |
| 256KB; L3 using shared design, is on-chip All cores | | | | Of course, the code selection are not limited to these |
| share. | | | | two states, the project Dell Inspiron 8000 battery can |
| (2) integrate the memory controller (IMC )---- move | | | | also be a map from their home or other place names |
| from the chipset CPU chip, multi-channel DDR3 | | | | can be found on the map as a code. In my impression, |
| memory, significantly reducing memory read latency, | | | | the Chinese team is responsible for some of the items |
| memory bandwidth is significantly Sony VGP-BPL2 | | | | on the used as the Pearl River (Zhujiang), Yellow River |
| battery up to threefold. | | | | (Yellow River), O'River (Ou River) and so on, because |
| (3) QPI ---- "fast-track Internet", replace the front-end | | | | the project is regional, it is only used in internal |
| bus (FSB) as a point to point connection technology, 20 | | | | communication Therefore, the code is not for the |
| bit wide of the QPI connections per second bandwidth | | | | public aware of the many. |
| of up to astonishing 25.6GB, far from being | | | | |